On-the-Fly Programmable Hardware for Networks
نویسندگان
چکیده
Ongoing research in adaptive protocols and active networks has presumed that flexibility is offered exclusively through software systems, and the performance implications have generated considerable skepticism. The programmable Protocol Processing Pipeline (P4) exploits the dynamic reconfigurability of RAM based Field Programmable Gate Arrays (FPGAs) to provide both hardware performance and dynamic functionality to network components. We use forward error correction (FEC) as an example of a protocol processing function. Our measurements show that P4 is able to process the data stream at OC-3 (155 Mbps) link rate, and consequently improve TCP performance in noisy environments. Comments University of Pennsylvania Department of Computer and Information Science Technical Report No. MSCIS-98-04. This technical report is available at ScholarlyCommons: http://repository.upenn.edu/cis_reports/49 ! " $#% '& () +*, )./ 0 1(2 3 465 798;:=A@!>CB DE:;FG>CH BJICKLHM>1NPOM>CHRQTSVU'WX:YNPO Z :\[]N?^?:;_ ` NPaEB U'b'[]NPaEWX[!cd>C_VKL^P>eN?KL^]bCfMg!H :\hLaE^?[]:\N9biKCj klaEH H [mb 8Yhe>CH :n>Co p q rts u0ptvew x x-y{z |Mxe} }6y"xtsLz ~1ew v pt y{z |Mxe} }6y"xtsLz
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